The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Jul. 23, 2020
Applicant:

Vermon SA, Tours, FR;

Inventors:

Claire Bantignies, Tours, FR;

Guillaume Férin, Truyes, FR;

Assignee:

VERMON SA, Tours, FR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); B81B 7/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00095 (2013.01); B81B 7/0006 (2013.01); B81B 2201/0271 (2013.01); B81B 2207/012 (2013.01); B81B 2207/07 (2013.01); B81C 2201/0194 (2013.01); B81C 2203/0792 (2013.01);
Abstract

A method of manufacturing a panel transducer scale package includes securing acoustic components at predetermined locations on a first carrier substrate with a first surface of the acoustic components positioned adjacent to the first carrier substrate. ASIC components are also secured at predetermined locations on the first carrier substrate with a first surface of the ASIC components positioned adjacent to the first carrier substrate. Photoresist resin is applied over the acoustic components and the ASIC components such that a second surface of the acoustic components is left exposed from the photoresist resin. The first carrier substrate is removed to expose the first surface of the acoustic components and the first surface of the ASIC components. A buildup layer is formed including electrical pathways between each of the acoustic components and the ASIC components, and the photoresist resin is removed.


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