The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Dec. 15, 2021
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Yoshiaki Satou, Kyoto, JP;

Shota Yamada, Shiga, JP;

Masashi Murakami, Kyoto, JP;

Yutaka Hirose, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/63 (2023.01); H04N 25/59 (2023.01); H04N 25/62 (2023.01); H04N 25/70 (2023.01); H04N 25/76 (2023.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H04N 25/63 (2023.01); H01L 27/146 (2013.01); H01L 27/14612 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 27/14665 (2013.01); H04N 25/59 (2023.01); H04N 25/62 (2023.01); H04N 25/70 (2023.01); H04N 25/76 (2023.01);
Abstract

An imaging device including a semiconductor substrate that includes a first impurity region; a photoelectric converter that is coupled to the first impurity region and that converts light into charges; a capacitor that includes a first terminal and a second terminal, the first terminal coupled to the first impurity region; voltage supply circuitry coupled to the second terminal; a first transistor including the first impurity region as a source or a drain; and control circuitry. The control circuitry is programmed to cause the voltage supply circuitry to supply a first voltage in a first period, and to cause the voltage supply circuitry to supply a second voltage different from the first voltage in a second period continuous to the first period, the first transistor being in on-state in the first period, the first transistor being in off-state in the second period.


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