Multiple pll system with common and difference mode loop filters

Abstract

A plurality of Phase Locked Loops, PLL (), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL () is connected to a phase error averaging circuit (), which calculates an average phase error (C), and distributes it back to each PLL (). In each PLL (), two loop filters () with different bandwidths are deployed. A lower bandwidth, high DC gain, common mode loop operates on the average phase error, and forces the PLL outputs (H) to track the phase of the common reference signal. A high bandwidth, difference mode loop operates on the difference between the local phase error (B) and the average phase error (C) to suppress phase differences between PLL outputs, minimizing interaction between them. The reference noise contribution at the output is controlled by the common mode loop, which can have a low bandwidth. The reference noise contribution and oscillator interaction suppression are thus independently controlled.