The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Jan. 26, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seungryul Lee, Seoul, KR;

Yongseung Kim, Seongnam-si, KR;

Jungtaek Kim, Yongin-si, KR;

Pankwi Park, Incheon, KR;

Dongchan Suh, Yangju-si, KR;

Moonseung Yang, Hwaseong-si, KR;

Seojin Jeong, Incheon, KR;

Minhee Choi, Suwon-si, KR;

Ryong Ha, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 29/0673 (2013.01); H01L 29/4238 (2013.01); H01L 29/785 (2013.01);
Abstract

An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.


Find Patent Forward Citations

Loading…