The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Mar. 27, 2019
Applicant:

Nitto Denko Corporation, Ibaraki, JP;

Inventors:

Ryota Mita, Ibaraki, JP;

Tomoaki Ichikawa, Ibaraki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 24/83 (2013.01); H01L 21/4853 (2013.01); H01L 21/565 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2221/68336 (2013.01); H01L 2224/29239 (2013.01); H01L 2224/29247 (2013.01); H01L 2224/29286 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/8384 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/0541 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10272 (2013.01);
Abstract

A manufacturing method includes the step of forming a diced semiconductor wafer () including semiconductor chips () from a semiconductor wafer (W) typically on a dicing tape (T). The diced semiconductor wafer () on the dicing tape (T) is laminated with a sinter-bonding sheet (). The semiconductor chips () each with a sinter-bonding material layer () derived from the sinter-bonding sheet () are picked up typically from the dicing tape (T). The semiconductor chips () each with the sinter-bonding material layer are temporarily secured through the sinter-bonding material layer () to a substrate. Through a heating process, sintered layers are formed from the sinter-bonding material layers () lying between the temporarily secured semiconductor chips () and the substrate, to bond the semiconductor chips () to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to individual semiconductor chips while reducing loss of the sinter-bonding material.


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