The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Sep. 04, 2020
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Oh-Hyun Kim, Gyeonggi-do, KR;

Sung-Hwan Ahn, Gyeonggi-do, KR;

Hae-Jung Park, Seoul, KR;

Tae-Hang Ahn, Seoul, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); H10B 12/00 (2023.01); H01L 21/768 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28562 (2013.01); H01L 21/28525 (2013.01); H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76879 (2013.01); H01L 21/76883 (2013.01); H01L 21/76897 (2013.01); H01L 27/10814 (2013.01); H01L 27/10855 (2013.01); H01L 27/10885 (2013.01); H01L 27/10888 (2013.01); H01L 27/10826 (2013.01);
Abstract

A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.


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