Display driver adjusting output timings of driving voltages at output channels

Abstract

A display driver is provided. A designation of an output timing at each of first and koutput channels is received, and first and second delay pulse signals are generated at respective output timings of the first and the koutput channels. First to kfirst direction delay shift signals where a first delay pulse signal is present after a delay increased for each output channel from the first toward the koutput channel are generated. First to ksecond direction delay shift signals where a second delay pulse signal is present after the delay increased for each output channel from the ktoward the first output channel are generated. One whose timing at which a delay pulse signal is present is earlier is selected from each of the direction delay shift signals corresponding to the same output channel, and set as first to koutput timing signals.