The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Sep. 15, 2021
Applicants:

Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yongxian Xie, Beijing, CN;

Tong Yang, Beijing, CN;

Feng Qu, Beijing, CN;

Fengzhen Lv, Beijing, CN;

Xianjie Shao, Beijing, CN;

Rui Ma, Beijing, CN;

Rui Li, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); G11C 19/287 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01);
Abstract

The present disclosure provides a shift register, a gate driving circuit and a display panel, and belongs to the field of display technology. The shift register of the present disclosure includes: an input circuit configured to precharge and reset a pull-up node; one pull-down control circuit being electrically connected to one pull-down circuit through a pull-down node; the pull-down control circuit being configured to control a potential at the pull-down node under a first power voltage; each pull-down circuit being configured to pull down the potential at the pull-down node in response to a potential at the pull-up node; an output circuit configured to output a clock signal through a signal output terminal in response to the potential at the pull-up node; one first noise reduction circuit connected to one pull-down node.


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