The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Aug. 31, 2020
Applicant:

Xioxia Corporation, Tokyo, JP;

Inventor:

Shigehiro Yamakita, Yokkaichi Mie, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/50 (2023.01); H10B 43/10 (2023.01); H10B 43/40 (2023.01); G11C 16/04 (2006.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/50 (2023.02); H10B 43/10 (2023.02); H10B 43/40 (2023.02); G11C 16/0483 (2013.01); H10B 43/27 (2023.02);
Abstract

A semiconductor memory device includes a substrate including a first region, as second region, a third region and a fourth regions, the first region including a memory cell array, the second region including a circuit for controlling the memory cell array, the third region separating the first region and the second region, and the fourth region surrounding the third region, a first transistor provided in the second region, a second transistor provided in the third region between the first region and the first transistor, a third transistor provided in the third region between the first transistor and the second transistor, and a first insulating layer including a first portion disposed above the first to third transistors, and a second portion disposed in contact with the substrate between the second transistor and the third transistor.


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