The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2023
Filed:
Feb. 28, 2020
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventor:
Tadashi Yamaguchi, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 21/285 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/28518 (2013.01); H01L 27/11573 (2013.01); H01L 29/45 (2013.01); H01L 29/66795 (2013.01); H01L 29/66833 (2013.01); H01L 29/7851 (2013.01); H01L 29/792 (2013.01);
Abstract
In a semiconductor device having MONOS memories configured by fin-type MISFETs, an increase in parasitic capacitance between wirings accompanying miniaturization of the semiconductor device is prevented, and the reliability of the semiconductor device is improved. In a memory cell array in which a plurality of MONOS type memory cells formed on fins are arranged, source regions formed on the plurality of fins arranged in a short direction of the fin are electrically connected to each other by one epitaxial layer straddling the fins.