The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Aug. 06, 2020
Applicant:

Kioxia Corporation, Minato-ku, JP;

Inventors:

Genki Kawaguchi, Yokkaichi, JP;

Yasuhito Yoshimizu, Yokkaichi, JP;

Yusuke Shima, Yokkaichi, JP;

Assignee:

Kioxia Corporation, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); G11C 16/04 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); G11C 5/025 (2013.01); G11C 5/06 (2013.01); G11C 16/0408 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); H01L 27/11582 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a plurality of first insulating layers; a plurality of first interconnect layers stacked alternately with the first insulating layers; a plurality of second interconnect layers arranged adjacently to the first interconnect layers; and a separation region including a plurality of first portions provided between the first interconnect layers and the second interconnect layers, and a plurality of second portions protruding from an outer periphery of each of the first portions. The second portions are linked to each other. The first interconnect layers and the second interconnect layers are separated from each other by the first portions and the linked second portions.


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