The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Nov. 10, 2021
Applicant:

Realtek Semiconductor Corp., HsinChu, TW;

Inventors:

Yi-Chun Hsieh, HsinChu, TW;

Yi-Chun Hsieh, HsinChu, TW;

Pei-Tse Chiang, HsinChu, TW;

Chih-Kai Chien, HsinChu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 25/49 (2006.01); H03K 9/08 (2006.01); H03M 5/08 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0079 (2013.01); H03K 9/08 (2013.01); H03M 5/08 (2013.01); H04L 7/0016 (2013.01); H04L 25/4902 (2013.01);
Abstract

The present invention provides a receiver including a sampling circuit, a data sampling point selection circuit and a determination circuit. The sampling circuit is configured to use a clock signal to sample an input signal to generate a sampled signal, wherein a frequency of the clock signal is greater than a frequency of the input signal. The data sampling point selection circuit is configured to filter start point data to generate a filtered start point data, and to generate a data sampling point by adding an offset to the filtered start point data, wherein the start point data corresponds to a time point that a sampled value of sampled signal starts to change. The determination circuit is configured to refer to a sampled value corresponding to the data sampling point in the sampled signal to determine a logical value of a digital output signal corresponding to the input signal.


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