The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Oct. 01, 2021
Applicant:

Psemi Corporation, San Diego, CA (US);

Inventors:

Ravindranath D. Shrivastava, San Diego, CA (US);

Fleming Lam, San Diego, CA (US);

Payman Shanjani, San Diego, CA (US);

Assignee:

PSEMI CORPORATION, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/40 (2015.01); H03F 3/24 (2006.01); H03H 11/28 (2006.01);
U.S. Cl.
CPC ...
H04B 1/40 (2013.01); H03F 3/245 (2013.01); H03H 11/28 (2013.01); H03F 2200/294 (2013.01); H03F 2200/451 (2013.01);
Abstract

An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.


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