The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Nov. 18, 2021
Applicant:

Microchip Technology Inc., Chandler, AZ (US);

Inventors:

Jonathan W. Greene, Palo Alto, CA (US);

Marcel Derevlean, Barsinghausen, DE;

Assignee:

Microchip Technology Inc., Chandler, AZ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17736 (2020.01); H03K 19/17728 (2020.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17728 (2013.01); H03K 19/17736 (2013.01); H03K 19/21 (2013.01);
Abstract

A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).


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