The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Apr. 03, 2020
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Yuya Kimura, Kanagawa, JP;

Hisashi Owa, Kanagawa, JP;

Takashi Nakamura, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/156 (2006.01); H03K 5/13 (2014.01); H03K 19/20 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1565 (2013.01); H03K 5/13 (2013.01); H03K 19/20 (2013.01); H03K 2005/00019 (2013.01);
Abstract

A circuit system is disclosed. In one example, the circuit system includes a clock tree circuit with multiple lanes to which a clock signal is distributed. A duty correction circuit is provided for each of the multiple lanes, and corrects a duty ratio of the clock signal. A clock gating circuit group has a clock gating circuit for each of the multiple lanes and receives, as input, the clock signal from the duty correction circuit. The clock gating circuit group starts output of the clock signal from each of a plurality of the clock gating circuits in a predetermined period. A variable delay circuit is provided in association with each of a plurality of the duty correction circuits and is capable of changing a delay time of a control signal that controls a timing of starting output of the clock signal from the clock gating circuit.


Find Patent Forward Citations

Loading…