The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Apr. 27, 2021
Applicant:

Infineon Technologies Llc, San Jose, CA (US);

Inventor:

Oren Shlomo, Haifa, IL;

Assignee:

INFINEON TECHNOLOGIES LLC, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/1252 (2006.01); H03K 5/153 (2006.01); G11C 7/20 (2006.01); G11C 7/02 (2006.01); H03K 17/22 (2006.01); G01K 7/18 (2006.01); G01K 7/20 (2006.01); G01R 19/25 (2006.01); G11C 7/14 (2006.01); H03K 5/24 (2006.01); G11C 7/10 (2006.01); H03K 5/19 (2006.01); H03K 17/24 (2006.01); G05F 1/648 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1252 (2013.01); G01K 7/183 (2013.01); G01K 7/20 (2013.01); G01R 19/2506 (2013.01); G05F 1/648 (2013.01); G11C 7/02 (2013.01); G11C 7/1039 (2013.01); G11C 7/14 (2013.01); G11C 7/20 (2013.01); H03K 5/153 (2013.01); H03K 5/19 (2013.01); H03K 5/2472 (2013.01); H03K 17/223 (2013.01); H03K 17/24 (2013.01);
Abstract

A voltage-glitch detection and protection circuit and method are provided. Generally, circuit includes a voltage-glitch-detection-block (GDB) and a system-reset-block coupled to the GDB to generate a reset-signal to cause devices in a chip including the circuit to be reset when a voltage-glitch in a supply voltage (VDD) is detected. The GDB includes a voltage-glitch-detector coupled to a latch. The voltage-glitch-detector detects the voltage-glitch and generates a PULSE to the system-reset-block and latch. The latch receives the PULSE and generates a PULSE_LATCHED signal to the system-reset-block to ensure the reset-signal is generated no matter a width of the PULSE. In one embodiment, the latch includes a filter and a sample and hold circuit to power the latch, and ensure the PULSE_LATCHED signal is coupled to the system-reset-block when a voltage to the GDB or to the latch drops below a minimum voltage due to the voltage-glitch.


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