The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Nov. 05, 2021
Applicant:

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventor:

Bruno Gailhard, Peypin, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/03 (2006.01); H03K 5/26 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01); G06F 1/06 (2006.01); G06F 1/08 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0315 (2013.01); G06F 1/06 (2013.01); G06F 1/08 (2013.01); H03K 5/00006 (2013.01); H03K 5/26 (2013.01); H03L 7/093 (2013.01); H03L 7/0995 (2013.01);
Abstract

A device for generating first clock signals includes first circuits, each including a ring oscillator delivering one of the first clock signals and being connected to a first node configured to receive a first current. A circuit selects one the first clock signals, and a phase-locked loop delivers a second signal which is a function of a difference between a frequency of the first selected clock signal and a set point frequency. Each first circuit supplies the first node with a compensation current determined by the second signal, when this first circuit delivers the selected clock signal and operates in controlled mode.


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