The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2023
Filed:
Sep. 22, 2022
Applicant:
Psemi Corporation, San Diego, CA (US);
Inventors:
Poojan Wagh, Sleepy Hollow, IL (US);
Kashish Pal, Reading, GB;
Assignee:
pSemi Corporation, San Diego, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); H03F 1/56 (2006.01); H03F 3/193 (2006.01); H03F 1/22 (2006.01); H03F 1/30 (2006.01); H03F 3/189 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0227 (2013.01); H03F 1/223 (2013.01); H03F 1/301 (2013.01); H03F 1/56 (2013.01); H03F 3/189 (2013.01); H03F 3/193 (2013.01); H03F 2200/18 (2013.01); H03F 2200/249 (2013.01); H03F 2200/453 (2013.01);
Abstract
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.