The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

May. 17, 2021
Applicant:

Exalos Ag, Schlieren, CH;

Inventors:

Antonino Francesco Castiglia, Schlieren, CH;

Marco Rossetti, Schlieren, CH;

Marco Malinverni, Schlieren, CH;

Marcus Pierre Dülk, Schlieren, CH;

Christian Velez, Schlieren, CH;

Assignee:

EXALOS AG, Schlieren, CH;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/00 (2006.01); H01S 5/40 (2006.01); H01S 5/042 (2006.01); H01S 5/22 (2006.01); H01S 5/0625 (2006.01); H01S 5/10 (2021.01); H01S 5/20 (2006.01); H01S 5/343 (2006.01);
U.S. Cl.
CPC ...
H01S 5/4031 (2013.01); H01S 5/042 (2013.01); H01S 5/0625 (2013.01); H01S 5/1021 (2013.01); H01S 5/1039 (2013.01); H01S 5/2018 (2013.01); H01S 5/22 (2013.01); H01S 5/343 (2013.01);
Abstract

An edge-emitting semiconductor laser diode chipwith mutually opposed front and back end facet mirrors. First and second ridgesextend between the chip end facetsto define first and second waveguides in an active region layer. Low and high slope efficiency laser diodes are thus formed that are independently drivable by respective electrode pairsand. The single chipthus incorporates two laser diodes sharing a common heterostructure, one with low slope efficiency optimized for low power operation with good power stability against temperature variations and random threshold current fluctuations in the close-to-threshold power regime, and the other with high slope efficiency optimized for high wall plug efficiency operation at higher output powers when the chip is operating far above threshold.


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