The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2023
Filed:
Mar. 24, 2021
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 23/544 (2006.01); H10B 12/00 (2023.01); H10B 10/00 (2023.01); H01L 29/423 (2006.01); H01L 27/108 (2006.01); H01L 27/11 (2006.01); H10B 41/50 (2023.01); H01L 27/11548 (2017.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 23/544 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01); H01L 27/1116 (2013.01); H01L 29/4236 (2013.01); H01L 27/11548 (2013.01); H01L 2223/5446 (2013.01);
Abstract
A semiconductor memory element is provided. The semiconductor memory element includes a substrate including a memory cell region and a peripheral circuit region, an active region located in the memory cell region, a gate pattern buried in the active region, a conductive line disposed on the gate pattern, a first region including a plurality of peripheral elements placed in the peripheral circuit region, a dummy pattern buried in the peripheral circuit region, and a second region which includes the dummy pattern and does not overlap the first region.