The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Mar. 03, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seho You, Seoul, KR;

Kyounglim Suk, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/66 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/5226 (2013.01); H01L 23/66 (2013.01); H01L 24/20 (2013.01); H01L 24/16 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A semiconductor package is provided. The semiconductor package comprising a first redistribution structure comprising a first redistribution pattern; a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising a semiconductor substrate comprising a first surface and a second surface, a first back end of line (BEOL) structure on the first surface of the semiconductor substrate and comprising a first interconnect pattern, and a second BEOL structure on the second surface of the semiconductor substrate and comprising a second interconnect pattern; a molding layer covering a sidewall of the first semiconductor chip; a second redistribution structure on the first semiconductor chip and the molding layer and comprising a second redistribution pattern electrically connected to the second interconnect pattern.


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