The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Oct. 01, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jongsup Song, Hwaseong-si, KR;

Seolyoung Choi, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 25/16 (2023.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/367 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H01S 5/024 (2006.01); H01S 5/0234 (2021.01); H01S 5/02253 (2021.01);
U.S. Cl.
CPC ...
H01L 23/49827 (2013.01); H01L 23/13 (2013.01); H01L 23/367 (2013.01); H01L 23/49838 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/165 (2013.01); H01L 25/167 (2013.01); H01S 5/0234 (2021.01); H01S 5/02253 (2021.01); H01S 5/02469 (2013.01); H05K 1/112 (2013.01); H05K 1/181 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/73265 (2013.01);
Abstract

A wiring board includes: a metal plate having first and second surfaces opposite to each other, and having at least one through-hole penetrating through the first and second surfaces; at least one conductive via respectively disposed in the through-hole and spaced apart from the metal plate; an insulating structure including at least one through-insulating portion disposed between the through-hole and the conductive via, and a first insulating layer and a second insulating layer extending from the through-insulating portion and disposed in first regions surrounding the conductive via, on the first surface and the second surface, respectively; at least one first upper pad disposed on the first insulating layer and electrically connected to the conductive via; at least one first lower pad disposed on the second insulating layer and electrically connected to the conductive via; a second upper pad disposed on the first surface of the metal plate; and a second lower pad disposed on the second surface of the metal plate and electrically connected to the first upper pad through the metal plate.


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