The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Mar. 19, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Minjung Choi, Suwon-si, KR;

Jung-Hoon Han, Hwaseong-si, KR;

Jiho Kim, seoul, KR;

Young-Yong Byun, Seoul, KR;

Yeonjin Lee, Suwon-si, KR;

Jihoon Chang, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/31 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 23/58 (2006.01); H01L 23/29 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H01L 23/528 (2013.01); H01L 21/78 (2013.01); H01L 23/291 (2013.01); H01L 23/296 (2013.01); H01L 23/585 (2013.01); H01L 24/05 (2013.01); H01L 2224/0219 (2013.01); H01L 2224/0221 (2013.01); H01L 2224/02181 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05553 (2013.01);
Abstract

A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.


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