The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Apr. 23, 2021
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Rahul Mathur, Austin, TX (US);

Mudit Bhargava, Austin, TX (US);

Andy Wangkun Chen, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 11/4093 (2006.01); G11C 11/4094 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G11C 5/06 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01);
Abstract

Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.


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