The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Jun. 29, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seungju Kim, Suwon-si, KR;

Hyojin Choi, Seoul, KR;

In Huh, Seoul, KR;

Jeonghoon Ko, Hwaseong-si, KR;

Changwook Jeong, Busan, KR;

Younsik Park, Hwaseong-si, KR;

Joonwan Chai, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 20/00 (2019.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 30/3308 (2020.01); G06F 18/214 (2023.01);
U.S. Cl.
CPC ...
G06N 20/00 (2019.01); G06F 9/30036 (2013.01); G06F 9/3879 (2013.01); G06F 18/214 (2023.01); G06F 30/3308 (2020.01);
Abstract

An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.


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