The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Sep. 29, 2022
Applicant:

Chiplego Technology (Shanghai) Co., Ltd, Shanghai, CN;

Inventors:

Sheau Jiung Lee, Shanghai, CN;

Hongyu Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 13/362 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
G06F 13/3625 (2013.01); G06F 1/10 (2013.01);
Abstract

A bus pipeline structure comprises: an n-channel multiplexer at a transmitting end works in an n times of clock domain of a transmitting chiplet; the n-channel multiplexer sends a data flow from the transmitting chiplet to an n-channel de-multiplexer at a receiving end, the n-channel de-multiplexer inputs the received data flow into a first register in an idle state among at least two registers at the receiving end, the first register outputs the received data flow to a receiving chiplet; after a receiving state machine at the receiving end determines that the n-channel de-multiplexer sends the received data flow to the first register, the receiving state machine at the receiving end sends a bus release flag to a transmitting state machine at the transmitting end, and the transmitting state machine receiving the bus release flag controls an n-channel multiplexer to transmit the data flow in a next clock cycle.


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