The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2023
Filed:
Sep. 17, 2021
Nvidia Corporation, Santa Clara, CA (US);
Sailendra Chadalavada, Saratoga, CA (US);
Venkat Abilash Reddy Nerallapally, San Jose, CA (US);
Jaison Daniel Kurien, Bangalore, IN;
Bonita Bhaskaran, San Jose, CA (US);
Milind Sonawane, Santa Clara, CA (US);
Shantanu Sarangi, Saratoga, CA (US);
Purnabha Majumder, Lafayette, CA (US);
NVIDIA CORPORATION, Santa Clara, CA (US);
Abstract
During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.