The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Feb. 07, 2022
Applicant:

Key Foundry Co., Ltd., Cheongju-si, KR;

Inventors:

Kwang Il Kim, Cheongju-si, KR;

Yang Beom Kang, Cheongju-si, KR;

Jung Hwan Lee, Cheongju-si, KR;

Min Kuck Cho, Cheongju-si, KR;

Hyun Chul Kim, Chilgok-gun, KR;

Assignee:

KEY FOUNDRY CO., LTD., Cheongju-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H10B 41/43 (2023.02); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H10B 41/10 (2023.02); H10B 41/44 (2023.02);
Abstract

A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.


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