The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Mar. 16, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Inkyoung Heo, Hwaseong-si, KR;

Hyo-Sub Kim, Seoul, KR;

Sohyun Park, Seoul, KR;

Taejin Park, Yongin-si, KR;

Seung-Heon Lee, Seoul, KR;

Youn-Seok Choi, Seoul, KR;

Sunghee Han, Hwaseong-si, KR;

Yoosang Hwang, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/482 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10814 (2013.01); H01L 21/7682 (2013.01); H01L 23/5329 (2013.01); H01L 27/10823 (2013.01); H01L 27/10855 (2013.01); H01L 27/10876 (2013.01); H01L 27/10885 (2013.01); H01L 21/76264 (2013.01); H01L 23/4821 (2013.01);
Abstract

A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.


Find Patent Forward Citations

Loading…