The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Sep. 04, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Masaharu Wada, Yokohama Kanagawa, JP;

Mutsumi Okajima, Yokkaichi Mie, JP;

Tsuneo Inaba, Kamakura Kanagawa, JP;

Shinji Miyano, Yokohama Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 27/108 (2006.01); G11C 11/407 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10808 (2013.01); H01L 27/1082 (2013.01); H01L 27/10832 (2013.01); H01L 27/10897 (2013.01); G11C 11/407 (2013.01);
Abstract

A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.


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