The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Jun. 18, 2021
Applicant:

Huawei Technologies Co., Ltd., Guangdong, CN;

Inventors:

Xiaolong Ma, Shanghai, CN;

Riqing Zhang, Shanghai, CN;

Stephane Badel, Leuven, BE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); B82Y 10/00 (2011.01); H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); B82Y 10/00 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66469 (2013.01); H01L 29/66787 (2013.01); H01L 29/7613 (2013.01); H01L 29/785 (2013.01);
Abstract

An embodiment of the invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove; and forming a source and a drain in a preset source drain area along the gate length direction.


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