The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Apr. 03, 2019
Applicant:

Corning Incorporated, Corning, NY (US);

Inventors:

Jin Su Kim, Seoul, KR;

Scott Christopher Pollard, Big Flats, NY (US);

Assignee:

CORNING INCORPORATED, Corning, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/15 (2006.01); H01L 21/50 (2006.01); H01L 23/36 (2006.01); H01L 23/538 (2006.01); H01L 23/66 (2006.01); H01L 23/00 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01);
U.S. Cl.
CPC ...
H01L 23/15 (2013.01); H01L 21/50 (2013.01); H01L 23/36 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 23/66 (2013.01); H01L 24/14 (2013.01); H05K 1/0206 (2013.01); H05K 1/0306 (2013.01);
Abstract

An electronic package assembly includes a glass substrate including an upper glass cladding layer, a lower glass cladding layer, a glass core layer coupled to the upper glass cladding layer and the lower glass cladding layer, where the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer, a first cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer, and a second cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer, a microprocessor positioned within the first cavity, and a micro-electronic component positioned within the second cavity.


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