The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Jul. 05, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Rajiv Joshi, Yorktown Heights, NY (US);

Sudipto Chakraborty, Plano, TX (US);

Alexander Fritsch, Esslingen, DE;

Holger Wetter, Weil im Schoenbuch, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); G11C 11/4074 (2006.01); G11C 11/4094 (2006.01); G11C 11/419 (2006.01); G11C 11/413 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 11/4074 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 11/413 (2013.01); G11C 11/419 (2013.01);
Abstract

A singled ended current sense amplifier circuit including an input stage having a bitline node, a sense node and a feedback circuit comprising a feedback inverter configured to provide an amplified voltage from the bitline node. The feedback inverter may include first and second NMOS transistors serially connected to a feedback node and first and second PMOS transistors serially connected to the feedback node. The feedback circuit may include a third NMOS transistor having a gate terminal connected to the feedback node and a drain terminal connected to the sense node. The input stage may include a third PMOS transistor operating as a current source to generate a sense current which flows in a current sensing path between the sense node and the bitline node. The input stage may act as a regulator to keep the voltage at the bitline node constant.


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