The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Nov. 20, 2021
Applicant:

Netlist, Inc., Irvine, CA (US);

Inventors:

Hyun Lee, Ladera Ranch, CA (US);

Jayesh R. Bhakta, Cerritos, CA (US);

Chi She Chen, Walnut, CA (US);

Jeffery C. Solomon, Irvine, CA (US);

Mario Jesus Martinez, Laguna Niguel, CA (US);

Hao Le, Santa Ana, CA (US);

Soon J. Choi, Irvine, CA (US);

Assignee:

Netlist, Inc., Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/08 (2016.01); G06F 12/0871 (2016.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G06F 13/28 (2006.01); G06F 13/10 (2006.01); G06F 12/06 (2006.01); G06F 12/0897 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 3/061 (2013.01); G06F 3/068 (2013.01); G06F 3/0685 (2013.01); G06F 12/0638 (2013.01); G06F 12/08 (2013.01); G06F 12/0871 (2013.01); G06F 13/10 (2013.01); G06F 13/28 (2013.01); G11C 7/1072 (2013.01); G06F 3/0656 (2013.01); G06F 3/0688 (2013.01); G06F 12/0897 (2013.01); G06F 2206/1014 (2013.01); G06F 2212/205 (2013.01); G06F 2212/214 (2013.01); G06F 2212/313 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7208 (2013.01);
Abstract

A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.


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