The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Nov. 24, 2020
Applicant:

Dell Products, Lp, Round Rock, TX (US);

Inventors:

John Christopher Beckett, New Braunfels, TX (US);

Mukund P. Khatri, Austin, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/177 (2006.01); G06F 9/00 (2006.01); G06F 9/445 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 9/4401 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/44505 (2013.01); G06F 9/30079 (2013.01); G06F 9/3877 (2013.01); G06F 9/4403 (2013.01); G06F 9/505 (2013.01);
Abstract

A basic input/output system provides an interface for a core aggregation layout that identifies a grouping of processor cores into core aggregations, wherein each of the core aggregations is associated with a maximum allowable C-state. A processor may monitor an information handling system during operation of an application to gather data associated with latency sensitivity of the application, update the core aggregation layout based on the data gathered during the operation of the application, and pin a thread for execution to one of the processor cores based on the latency sensitivity of the application and the maximum allowable C-state.


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