The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Apr. 15, 2022
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Harish Srinivasan, Sammamish, WA (US);

Robert C. Combs, Redmond, WA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06F 1/3287 (2019.01); G06F 1/3203 (2019.01); G06F 1/3296 (2019.01); G06F 1/3228 (2019.01); G06F 1/3234 (2019.01); G06F 11/34 (2006.01); G06F 1/26 (2006.01); G06F 1/3209 (2019.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/266 (2013.01); G06F 1/3203 (2013.01); G06F 1/3209 (2013.01); G06F 1/3228 (2013.01); G06F 1/3234 (2013.01); G06F 1/3278 (2013.01); G06F 1/3296 (2013.01); G06F 11/3048 (2013.01); G06F 11/3051 (2013.01); G06F 11/3409 (2013.01); G06F 9/3869 (2013.01); G06F 9/4881 (2013.01); G06F 9/544 (2013.01); G06F 11/3423 (2013.01); Y02D 10/00 (2018.01); Y02D 30/50 (2020.08);
Abstract

A supervisory control system provides power management in an electronic device by providing timeout periods for a hardware component to lower levels of the operating system such as a power management arbitrator and/or a hardware interface controller. The power management arbitrator and/or hardware interface controller transition at least a portion of a hardware component to a lower-power state based on monitored activity information of the hardware component. The supervisory control system may further provide wakeup periods to the power management arbitrator and/or a hardware interface controller to determine whether the hardware component should be transitioned to a higher-power state at the end of the wakeup period if the hardware component satisfies a transition condition.


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