The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2023
Filed:
Nov. 01, 2019
Applicant:
Raytheon Company, Waltham, MA (US);
Inventors:
Christine Frandsen, Santa Barbara, CA (US);
John J. Drab, Santa Barbara, CA (US);
Andrew Clarke, Santa Barbara, CA (US);
Assignee:
RAYTHEON COMPANY, Waltham, MA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H05K 1/03 (2006.01); H05K 3/40 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 1/115 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H05K 1/0306 (2013.01); H05K 3/4038 (2013.01); H05K 3/4623 (2013.01);
Abstract
A through-wafer via substrate includes a substrate having an intermediate layer and a bonding layer formed on a surface of the intermediate layer. A via cavity extends through the bonding layer and into the intermediate layer, and a stress buffer liner is deposited directly on inner sidewalls and a base of the via cavity. An electrically conductive through-wafer via is disposed in the via cavity such that the stress buffer liner is interposed completely between the intermediate layer and the through-wafer via.