The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2023
Filed:
Jan. 14, 2022
Amplexia, Llc, Durham, NC (US);
Stephen R. Fairbanks, Mesa, AZ (US);
Amplexia, LLC, Durham, NC (US);
Abstract
Integrated circuits with enhanced EOS/ESD robustness and methods of designing same. One such integrated circuit includes a plurality of input/output pads, a positive voltage rail, a ground voltage rail, a collection of internal circuits representing the operational core of the integrated circuit, a plurality of input/output buffering circuits connected as inputs and outputs to the internal circuits, wherein the internal circuits and the input/output buffering circuits comprise functional devices, and a plurality of EOS/ESD protection circuits interconnected with the input/output pads to limit ESD voltage and/or shunt ESD current away from the functional devices. At least one of the EOS/ESD protection circuits is a MOSFET. The MOSFET has a source region having an accompanying ohmic contact. The MOSFET further has a rectifying junction contact in place of a drain region and accompanying ohmic contact.