The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Jan. 29, 2020
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventor:

Davide Giuseppe Patti, Mascalucia, IT;

Assignee:

STMICROELECTRONICS S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/8236 (2006.01); H01L 21/8258 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/78 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0883 (2013.01); H01L 21/8236 (2013.01); H01L 21/8258 (2013.01); H01L 29/16 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/66712 (2013.01); H01L 29/7786 (2013.01); H01L 29/781 (2013.01); H03K 17/6871 (2013.01);
Abstract

The power device is formed by a D-mode HEMT and by a MOSFET in cascade to each other and integrated in a chip having a base body and a heterostructure layer on the base body. The D-mode HEMT includes a channel area formed in the heterostructure layer; the MOSFET includes a first and a second conduction region formed in the base body, and an insulated-gate region formed in the heterostructure layer, laterally and electrically insulated from the D-mode HEMT. A first metal region extends through the heterostructure layer, laterally to the channel area and in electrical contact with the channel area and the first conduction region.


Find Patent Forward Citations

Loading…