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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11658056 B1

PDFFull Text
Date of Patent:
May. 23, 2023

Filed:

Apr. 08, 2020

Technique for handling diced wafers of integrated circuits

Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Antonius Hendrikus Jozef Kamphuis, Lent, NL;

Johannes Cobussen, Beuningen, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:

Philip C Tucker

Assistant Examiner:

Nickolas R Harm

Int. Cl.
CPC ...
B29C 65/00 (2006.01); H01L 21/683 (2006.01); H01L 21/677 (2006.01); H01L 23/00 (2006.01); C09J 7/20 (2018.01); B29C 65/50 (2006.01); B29C 65/52 (2006.01); B29C 65/58 (2006.01); B29C 65/56 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6836 (2013.01); C09J 7/20 (2018.01); H01L 21/6779 (2013.01); H01L 21/67763 (2013.01); H01L 24/01 (2013.01); B29C 65/50 (2013.01); B29C 65/526 (2013.01); B29C 65/565 (2013.01); B29C 65/58 (2013.01); H01L 21/6838 (2013.01);
Abstract

A technique for handling an integrated circuit tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit tape assembly on a film frame carrier (FFC) frame, stretching the dicing tape while on the FFC frame, and securing the stretched dicing tape by engaging a spring ring with the dicing tape and FFC frame. Adjacent integrated circuits are thereby inhibited from colliding during shipment or storage for subsequent processing.

Find Patent Forward Citations

Kamphuis, Antonius Hendrikus Jozef. (2023). Technique for handling diced wafers of integrated circuits (U.S. Patent No. 11658056). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11658056

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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