The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Jul. 23, 2021
Applicant:

Imagination Technologies Limited, Kings Langley, GB;

Inventor:

Sam Elliott, London, GB;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G01R 31/3183 (2006.01); G06F 30/33 (2020.01); G06F 30/3323 (2020.01); G06F 30/337 (2020.01); G06F 119/16 (2020.01); G06F 111/12 (2020.01); G06F 115/02 (2020.01); G06F 30/3308 (2020.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G01R 31/318314 (2013.01); G06F 30/337 (2020.01); G06F 30/3323 (2020.01); G06F 30/3308 (2020.01); G06F 2111/12 (2020.01); G06F 2115/02 (2020.01); G06F 2119/16 (2020.01);
Abstract

A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component is configured to produce a specific output transaction with a causal deterministic relationship to the specific input transaction.


Find Patent Forward Citations

Loading…