The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

May. 09, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seok-Ju Yoon, Yongin-si, KR;

Nak-Woo Sung, Yongin-si, KR;

Seung-Chull Suh, Seongnam-si, KR;

Taek-Ki Kim, Seongnam-si, KR;

Jae-Joon Yoo, Incheon, KR;

Eun-Ok Jo, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/329 (2019.01); G06F 1/3228 (2019.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01); G06F 15/167 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 1/329 (2013.01); G06F 1/324 (2013.01); G06F 1/3228 (2013.01); G06F 1/3296 (2013.01);
Abstract

A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.


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