The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Dec. 04, 2020
Applicants:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Jean-Philippe Reynard, Grenoble, FR;

Sylvie Del Medico, Crolles, FR;

Philippe Brun, Meylan, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 43/02 (2006.01); H01L 43/12 (2006.01); H01L 27/22 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/16 (2013.01); H01L 27/222 (2013.01); H01L 27/24 (2013.01); H01L 43/02 (2013.01); H01L 43/12 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01);
Abstract

A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.


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