The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Mar. 13, 2020
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Katsuhiko Hanzawa, Kanagawa, JP;

Yoshikazu Nitta, Park Ridge, NJ (US);

Hirotaka Murakami, Park Ridge, NJ (US);

Kazumasa Nishimura, Fukuoka, JP;

Pude Mark, Park Ridge, NJ (US);

Christopher Moule Eric, Park Ridge, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 25/75 (2023.01); H01L 27/146 (2006.01); H04N 25/46 (2023.01); H04N 25/778 (2023.01); G01S 7/4863 (2020.01);
U.S. Cl.
CPC ...
H04N 25/75 (2023.01); H04N 25/46 (2023.01); H04N 25/778 (2023.01); G01S 7/4863 (2013.01); H01L 27/14641 (2013.01); H01L 27/14645 (2013.01);
Abstract

A solid-state image capturing element includes a pair of first floating diffusion layers arranged in a direction perpendicular to a predetermined direction and a pair of second floating diffusion layers arranged in the perpendicular direction and adjacent to the pair of first floating diffusion layers in the predetermined direction. The element includes a first connection circuit configured to select at least one of the pair of first floating diffusion layers and to connect the selected first floating diffusion layer to a predetermined first wire; a second connection circuit configured to select at least one of the pair of second floating diffusion layers and to connect the selected second floating diffusion layer to the first wire; and an output circuit configured to output a signal according to an amount of charge of at least one of the pair of first floating diffusion layers or the pair of second floating diffusion layers.


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