The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Jul. 10, 2020
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventors:

Keigo Nakazawa, Tokyo, JP;

Kazuhiro Saito, Tokyo, JP;

Tetsuya Itano, Sagamihara, JP;

Kazuo Yamazaki, Yokohama, JP;

Hideo Kobayashi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/378 (2011.01); H04N 25/617 (2023.01); H01L 27/146 (2006.01); G06T 7/55 (2017.01); H04N 25/67 (2023.01); H04N 25/75 (2023.01); H04N 25/771 (2023.01); H04N 25/778 (2023.01);
U.S. Cl.
CPC ...
H04N 25/617 (2023.01); G06T 7/55 (2017.01); H01L 27/14603 (2013.01); H04N 25/67 (2023.01); H04N 25/75 (2023.01); H04N 25/771 (2023.01); H04N 25/778 (2023.01); G06T 2207/30252 (2013.01);
Abstract

An embodiment includes: a semiconductor substrate including a pixel well region and a peripheral well region; a pixel ground line arranged above the pixel well region; a pixel well contact between the pixel ground line and the pixel well region; pixels arranged to form columns in the pixel well region; a reference signal generation circuit arranged in the peripheral well region; and comparator units arranged in the peripheral well region, provided to respective columns, and each configured to receive the pixel signal from the pixels on a corresponding column and the reference signal. Each comparator unit includes a comparator having a first input node that receives the pixel signal and a second input node that receives the reference signal, a first capacitor unit between the reference signal generation circuit and the second input node, and a second capacitor unit between the second input node and the pixel ground line.


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