The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Jun. 14, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Sergej Markmann, Bochum, DE;

Gian R. von Salis, Aeugst a. A., CH;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03H 9/02 (2006.01); G06N 10/00 (2022.01); H01L 41/29 (2013.01); H03H 3/08 (2006.01); H03H 9/145 (2006.01); H03H 9/25 (2006.01);
U.S. Cl.
CPC ...
H03H 9/02 (2013.01); G06N 10/00 (2019.01); H01L 41/29 (2013.01); H03H 3/08 (2013.01); H03H 9/02685 (2013.01); H03H 9/02897 (2013.01); H03H 9/14552 (2013.01); H03H 9/25 (2013.01); H03H 2009/02165 (2013.01);
Abstract

A surface acoustic wave resonator device comprises a substrate supporting: a gateable, electrically conducting layer; an interdigital transducer (IDT); a reflector grating that comprises a plurality of electrically separated fingers; a main ohmic contact; and a gate element. The IDT is configured to be connectable to a ground. The conducting layer is configured to be connectable to the ground via the main ohmic contact, while each of said fingers is electrically connected to a lateral side of the conducting layer. This defines a gateable channel, which extends from the fingers to the ground via the conducting layer and the main ohmic contact. The gate element is electrically insulated from the conducting layer. The gate element is configured to allow an electrical impedance of the gateable channel to be continuously tuned by applying a voltage bias to this gate element with respect to the ground, in operation of the device.


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