The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Aug. 13, 2020
Applicant:

Nanowave Technologies Inc., Etobicoke, CA;

Inventors:

Trevor James Hall, Ottawa, CA;

Charles William Tremlett Nicholls, Nepean, CA;

Boris Spokoinyi, Kanata, CA;

Mehedi Hasan, Ottawa, CA;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03B 17/00 (2006.01); H03L 7/081 (2006.01); H03L 7/087 (2006.01); H04B 10/50 (2013.01); H03L 7/00 (2006.01);
U.S. Cl.
CPC ...
H03B 17/00 (2013.01); H03L 7/00 (2013.01); H03L 7/081 (2013.01); H03L 7/087 (2013.01); H03L 7/0816 (2013.01); H04B 10/50 (2013.01); H03B 2200/0044 (2013.01);
Abstract

An optoelectronic oscillator (OEO) including a drift compensation circuit is provided. The OEO includes a set of optical domain components communicatively coupled with a set of RF domain components. The RF domain components include a mode selection filter, a phase locked loop (PLL) and a drift compensation circuit communicatively coupled between the mode selection filter and the PLL. The mode selection filter provides a mode selection result to the drift compensation circuit. The drift compensation circuit phase modulates the mode selection result in a vector based coordinate system to maintain a drift compensated mode selection result within a locking bandwidth of the PLL, and to minimize phase shifting from accumulating phase drift. The PLL detects a phase difference between the drift compensated mode selection result and a reference signal, for use in maintaining the PLL in a phase lock with the reference signal, in particular over wide operational temperature ranges.


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