The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2023
Filed:
Oct. 12, 2022
Applicant:
Guobiao Zhang, Corvallis, OR (US);
Inventor:
Guobiao Zhang, Corvallis, OR (US);
Assignees:
HangZhou HaiCun Information Technology Co., Ltd., ZheJiang, CN;
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 25/065 (2023.01); G06F 15/80 (2006.01); G06F 9/30 (2018.01); G06F 21/56 (2013.01); G10L 15/22 (2006.01); G06K 9/62 (2022.01); G10L 15/183 (2013.01); G06F 18/21 (2023.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); G06F 9/3001 (2013.01); G06F 15/803 (2013.01); G06F 18/21 (2023.01); G06F 21/561 (2013.01); G10L 15/183 (2013.01); G10L 15/22 (2013.01); H01L 25/0657 (2013.01); G06F 2221/034 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01);
Abstract
A discrete three-dimensional (3-D) processor comprises stacked first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). In one preferred embodiment, the first and second dice are vertically stacked. In another preferred embodiment, the first and second dice are face-to-face bonded.