The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Jan. 12, 2021
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Hong Ki Moon, Gyeonggi-do, KR;

Seung Woo Lee, Gyeonggi-do, KR;

Dong Hee Han, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 8/18 (2006.01); G11C 29/12 (2006.01); G11C 7/10 (2006.01); G11C 29/46 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 7/106 (2013.01); G11C 8/18 (2013.01); G11C 29/12015 (2013.01); G11C 29/44 (2013.01); G11C 29/46 (2013.01);
Abstract

A memory device includes: a normal cell region suitable for storing write data and outputting read data; a parity cell region suitable for storing write parity bits and outputting read parity bits; a pattern generation circuit suitable for generating test data whose value is sequentially increased, and providing the test data as the write data, in a first test mode; an error correction circuit suitable for generating the write parity bits based on the write data, correcting an error of the read data based on the read parity bits, and outputting the error-corrected data; and an output circuit suitable for compressing the error-corrected data and outputting the compressed data, wherein the output circuit is further suitable for compressing the read parity bits output from the parity cell region to output the compressed data, in the first test mode.


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