The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Oct. 15, 2021
Applicant:

Tencent America Llc, Palo Alto, CA (US);

Inventors:

Xiang Zhang, Sunnyvale, CA (US);

Bing Jian, Cupertino, CA (US);

Lu He, Palo Alto, CA (US);

Haichao Zhu, Los Angeles, CA (US);

Shan Liu, San Jose, CA (US);

Kelin Liu, Thornhill, CA;

Weiwei Feng, Mountain View, CA (US);

Assignee:

TENCENT AMERICA LLC, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 11/20 (2006.01); G06T 19/00 (2011.01); G06T 7/60 (2017.01);
U.S. Cl.
CPC ...
G06T 11/203 (2013.01); G06T 7/60 (2013.01); G06T 19/00 (2013.01); G06T 2207/10028 (2013.01); G06T 2219/008 (2013.01);
Abstract

Aspects of the disclosure include methods, apparatuses, and non-transitory computer-readable storage mediums for generating a floor plan from a point cloud model. An apparatus includes processing circuitry that receives an input three-dimensional point cloud corresponding to a three-dimensional space. The processing circuitry determines a plurality of wall planes in the received input three-dimensional point cloud. The processing circuitry generates a plurality of line segments. Each line segment is generated by projecting a respective wall plane of the plurality of wall planes to a floor plane in the three-dimensional space. The processing circuitry represents the plurality of wall planes in the three-dimensional space using the plurality of line segments in a two-dimensional space corresponding to the floor plan. The processing circuitry adjusts the plurality of line segments in the two-dimensional space to improve the floor plan. The processing circuitry generates the floor plan based on the plurality of adjusted line segments.


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